(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for a re-deposition of a high compressive PECVD oxide after IMD CMP to prevent cracks.
(2) Description of the Prior Art
The continuing trend in the semiconductor industry of improving device performance by reducing device feature size has brought with it a continuing increase in device packing density. The continuing decrease of device feature size puts greater emphasis on the art of interconnecting device features and interconnecting devices within multiple device packages. It is therefore not uncommon to see devices that contain a relatively large number of overlaying layers of interconnecting metal lines. As the devices get smaller, however, their performance becomes more heavily dependent on the interconnections between them. Likewise, as the number of devices per chip increases, the area required to route the interconnect lines exceeds the area occupied by the devices. This normally leads to integrated circuit chips with multilevel interconnect schemes.
In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings. The first or lowest level of interconnect wires is typically formed as a first step in the process after which a second or overlying level of interconnect wires is deposited over the first level. The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contact. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure. The two levels of metal wires are connected by openings between the two layers that are filled with metal where the openings between the two layers are lined up with and match contact points in one or both of the levels of metal lines.
Previously used techniques to form multi-levels of wiring apply the technique of first forming the interconnect level metal in a first plane followed by forming the overlying level of interconnect wire in a second plane. This structure typically starts with the surface of a semiconductor substrate into which active devices have been created. These active devices can include bipolar transistors, MOSFET devices, doped regions that interconnect with other regions of the device while provisions may also have been provided to make interconnects with I/O terminals in the periphery of the device. The surface into which the pattern of interconnect lines of the first plane is formed may also be an insulation layer deposited over the surface of the substrate or a layer of oxide may first have been formed on the surface of the substrate. After the layer, into which the pattern of interconnecting wires has to be created, has been defined, the interconnecting pattern itself needs to be defined. This is done using conventional photolithographic techniques whereby the openings are made (in the layer) above the points that need to be contacted in the substrate. The openings, once created, may by lined with layers of material to enhance metal adhesion (to the sidewalls of the opening), the glue layer, or to prevent diffusion of materials into and from the substrate in subsequent processing steps, the barrier layer. For the barrier layer, a variety of materials can be used such as Ti/Tin:W (titanium/titanium nitride:tungsten), titanium-tungsten/titanium or titanium-tungsten nitride/titanium or titanium nitride or titamium nitride/titanium, silicon nitride (Si.sub.3 N.sub.4), tungsten, tantalum, niobium, molybdenum. The final phase in creating the first level of interconnect lines is to fill the created openings with metal, typically aluminum, tungsten or copper, dependent on the particular application and requirements and restrictions imposed by such parameters as line width, aspect ratio of the opening, required planarity of the surface of the deposited metal and others.
This process of line formation in overlying layers on metal can be repeated in essentially the same manner as just highlighted for the first layer of interconnecting wires. This process of forming sequential layers of interconnecting levels of wire is in many instances prone to problems and limitations. Copper has in recent times found more application in the use of metal wires due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper however exhibits the disadvantage of high diffusivity in common insulating materials such as silicon dioxide and oxygen-containing polymers. This leads to, for instance, the diffusion of copper into polyimide during high temperature processing of the polyimide resulting in severe erosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The erosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. The copper that is used in an interconnect may diffuse into the silicon dioxide layer causing the dielectric strength to become conductive and also decreasing the dielectric strength of the silicon dioxide layer. A copper diffusion barrier is therefore often required; silicon nitride is often applied as a diffusion barrier to copper. Silicon nitride however has a dielectric constant that is high compared to silicon dioxide thereby limiting the use of silicon nitride in encapsulating copper interconnect lines.
The first interconnection level, which contacts an integrated circuit device, typically contains the most narrow conductor and interconnection elements. Most commonly, first conductor levels have been formed from aluminum metal or aluminum metal alloys. Most commonly, first interconnection levels (i.e. first conductive contact studs) are formed of tungsten. As IC device dimensions have decreased while simultaneously maintaining and increasing demands for performance of the IC's, it has become increasingly important for conductor and interconnection elements within IC's to exhibit a high level of conductivity while simultaneously showing limited susceptibility to degradative phenomenon such as electromigration.
In fabricating a multilayer structure on the substrate to connect integrated circuits to one another, metal power and ground planes in the substrate are typically separated by layers of a dielectric such as a polyimide. A number of high-density semiconductor devices can in this manner be physically and electrically connected to a single substrate. Embedded in other dielectric layers are metal conductor lines with vias (holes) providing electrical connections between signal lines or to the metal power and ground planes. Adjacent layers are ordinarily formed so that the primary signal propagation directions are orthogonal to each other. While the size of aluminum interconnecting lines is of the sub-micron order, currents that flow through Al interconnecting lines are in the order of several hundred microamperes and current density is as high as 105 A/cm.sup.2. Mechanical stress in the order of 100 MPa is introduced in the interconnecting lines when the semiconductor is subjected to heat treatment in the VLSI manufacturing process.
Current technology frequently uses the application of a thin film of silicon dioxide over a surface thereby reducing potential damage to the surface. This thin film is created using Chemical Vapor Deposition (CVD) techniques whereby typically ozone-TEOS chemistry is used immediately followed by PECVD deposition of the silicon dioxide film. The CVD process has the disadvantage that it requires high temperatures, these high temperatures can damage the molecular structure of metal layers within the device. For this reason, Plasma Enhanced CVD (PECVD) is frequently used whereby the applied rf energy causes disassociation of the reactant gasses to a reaction zone close to the surface that is treated thereby creating a plasma of highly reactive ions. This reduces the energy that is required for a chemical reaction to take place and, as a consequence, the processing temperature required for the CVD process can be reduced. This makes the PECVD process of value for (for instance) the deposition of layers of insulation or dielectric over the surface of deposited layers of metal.
Where increased insulation is required, the Sub-Atmospheric CVD (SACVD) process is frequently used since this process (partly due to its slow deposition rate) allows good filling of gaps and spaces between metal lines. A typical SACVD process uses a temperature range of between 350 and 500 degrees C. with a pressure between about 20 and 700 torr. Because the PECVD deposition rate is relatively high, an insulation layer of considerable thickness is typically created by first forming the layer of PECVD over which the layer of SACVD is formed completing the required thickness of the insulation layer.
In the semiconductor industry, a body of work has been performed that relates to the formation of insulating and passivation layers whereby the choice of materials used, the sequence in which these layers are deposited and the particular processing conditions under which the layers are created are the parameters of choice in establishing the relative success of these processes. Efforts have for instance been invested in first creating a layer of SACVD over which a layer of PECVD is created. This process resulted in a layer that, when etched to create the pattern for the metal interconnect lines, results in a lateral etch into the relatively poor interface between the two layers resulting in an undesirable metal profile and, ultimately, reliability problems with the created metal lines.
FIG. 1 shows a Prior Art three metal level structure wherein 16, 20 and 24 form the first, second and third level of metal respectively. The plugs 18 and 22 connect the metal levels together while plug 14 connects the first level of metal 16 with the contact plug 26 that has been provided in the surface of the semiconductor substrate 10. Layers 12, 13 and 15 of dielectric separate the respective layers of metal. In the cross section that is shown in FIG. 1, the layer 12 of dielectric is referred to as the Intra Level Dielectric (ILD) while the layers 13 and 15 of dielectric are referred to as the Inter Metal Dielectric (IMD). The top layer 19 is typically an insulator and is deposited for protection of the semiconductor device from environmental damage during subsequent steps of device processing or packaging, this layer can for instance contain polyimide and is typically deposited to a thickness of several thousands of Angstrom. Layer 19 is patterned and etched to create an opening (not shown) in the layer 19, this opening aligns with the top metal pad 24. Electrical contact to the device and the underlying layers of metal is then established through this opening.
In creating a structure of a relatively large number of levels of metal, problems of planarity, adhesion, metal diffusion and others that have previously been highlighted can become particularly acute due to the very nature of the structure that is shown in FIG. 1. It is not uncommon to extend the number of metal layers in such a stack to 5 or more, this to meet the increased demands of device packaging density. The decrease in feature size that is also common for sub-micron devices further makes the creation of a large interconnect metal stack particularly challenging. The currently used 0.25 um design rule makes filling the gaps between created metal lines a critical issue. In creating a layer of IMD, a layer of PETEOS is frequently used that overlays a layer of SACVD, the two layers form one layer of IMD. It is critical for this layer of IMD that good adhesion is obtained along the surfaces where these two layers of PETEOS and SACVD make contact. Any lack of adhesion will ultimately result in peeling and reliability problems. A low stress interface between the two layers is therefore required. The invention addresses these problems of deposition of layers of IMD in the creation of a metal stack that has a large number of layers.